module regBank (
    input   logic           clk,
    input   logic           rst_n,
    
    input   logic   [4:0]   R_Addr_A,
    input   logic   [4:0]   R_Addr_B,
    input   logic           Write_Reg,
    input   logic   [4:0]   W_Addr,
    input   logic   [31:0]  W_Data,
    output  logic   [31:0]  R_Data_A,
    output  logic   [31:0]  R_Data_B
);


logic [31:0] regbank [31:0];

// reg0 read only
always_ff @( posedge clk, negedge rst_n ) begin
    if(!rst_n)
        regbank[0] <= 'd0;
end

// write
genvar i_regWrite;
generate
    for(i_regWrite = 1; i_regWrite < 32; i_regWrite = i_regWrite + 1) begin : label_regWrite
        always_ff @( posedge clk, negedge rst_n ) begin
            if(!rst_n) begin
                regbank[i_regWrite] <= 32'b0;
            end
            else if(Write_Reg &&(W_Addr == i_regWrite)) begin
                regbank[i_regWrite] <= W_Data;
            end
        end
    end
endgenerate

// read
always_comb begin
    R_Data_A = regbank[R_Addr_A];
    R_Data_B = regbank[R_Addr_B];
end


endmodule
